The present invention relates to a transistor logic circuit with multiple outputs and, more particularly but not exclusively, to connecting transistors to an intermediate node of a transistor logic circuit in order to implement additional logic functions.
The demand for low area and low power consumption are among the main issues in modern digital VLSI design. The advances of portable and consumer electronics are driving a need for new design technologies, which can achieve an alternative or improved design technique to standard Complementary Metal Oxide Semiconductor (CMOS) design. FIG. 1a shows a generalized structure of a logic function implemented in standard CMOS architecture. The logic function is implemented by two complementary transistor networks, the P-block 10 (which consists of p-type transistors) and the N-block 10 (which consists of n-type transistors). The two blocks are connected at a central node. One or more of the transistor inputs serve as logic inputs, X[n], while the central node serves as the logic output, OUT. In addition, each transistor network is connected to a respective root, where the root of P-block 10 is VDD (a high voltage, for example the positive supply voltage), and the root of N-block 20 is VSS (a low voltage, for example the negative supply voltage or ground).
One of the main drawbacks of standard complementary CMOS design structures is transistor redundancy. In standard CMOS architecture, complementary p-block and n-block arrangements of transistors are implemented in order to obtain a single logic function. All the transistors in the complementary CMOS structure are dedicated to implementation of the single logical function that is manifested in its output. The only node that is used as the output function is the central interconnection node of the n-block and p-block, while no use is made of the intermediate nodes.
The complementary structure of current CMOS architecture therefore results in a logic circuit which is inefficient in terms of transistor use, and, consequently, with high area and power requirements. In the following, parts that are the same as those in previous figures are given the same reference numerals and are not described again except as necessary for an understanding of the present embodiment.
U.S. Pat. Appl. No. 2004/0130349 of the present inventor, which is hereby incorporated by reference, presents a generalization of complementary CMOS architecture which is denoted Gate Diffusion Input (GDI) architecture. FIG. 1b shows a generalized structure of a logic function implemented in GDI architecture. As seen in FIG. 1b, in GDI the n-input CMOS structure is extended to an (n+2)-input GDI cell by introducing an input P instead of VDD in the P-block of the CMOS structure and an input N instead of VSS in the N-block.
The extended GDI implementation can be represented by the following logic expression:Out= F(x1 . . . xn)*N+F(x1 . . . xn)*P  (1)where F(x1 . . . xn) is the original output of CMOS circuit.
As can be seen, CMOS is a private case of GDI circuit in which N=Gnd (‘0’) and P=Vdd (‘1’). Like CMOS architecture, transistor use in general GDI architecture is inefficient. GDI consequently suffers from the same disadvantages.
There is thus a widely recognized need for, and it would be highly advantageous to have, a transistor logic circuit architecture devoid of the above limitations.